With the ever increasing feature growth and performance in each integrated circuit device generation, there is a need to correspondingly shrink the feature sizes of integrated circuit die interconnects and package substrate to provide higher performance in cost-optimized die sizes. This scaling phenomenon leads to the use of complex design layouts and manufacturing techniques in order to form reliable interconnect structures having suitable electrical and mechanical properties. It has proven difficult to continue to shrink the feature size of the interconnect structures while forming a reliable solder connection between the die and substrate.